Fault tolerant computer architecture
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Author
Publication
2009 - Morgan & Claypool Publishers, San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA), California
Language
English
Word Count
0 words, Guess
Page Count
0 pages
Physical Format
Electronic resource
Identifiers
- Internet Archivefaulttolerantcom00sori
- Internet Archivefaulttolerantcom00sori_826
- ISBN-139781598299540
- ISBN-139781598299533
- ISBN-101598299549
and 4 more
- ISBN-101598299530
- Better World Books9781598299533
- Better World Books9781598299540
- Open LibraryOL27038278M
Classifications
- DDC004.2
- LCCQA76.9.F38 S674 2009
Alternate Titles
- Synthesis digital library of engineering and computer science.
Description
For many years, most computer architects have pursued one primary goal: performance. Architects have translated the ever-increasing abundance of ever-faster transistors provided by Moore's law into remarkable increases in performance. Recently, however, the bounty provided by Moore's law has been accompanied by several challenges that have arisen as devices have become smaller, including a decrease in dependability due to physical faults. In this book, we focus on the dependability challenge and the fault tolerance solutions that architects are developing to overcome it. The two main purposes of this book are to explore the key ideas in fault-tolerant computer architecture and to present the current state-of-the-art--over approximately the past 10 years--in academia and industry.
Series Statement
- Synthesis lectures on computer architecture -- # 5
Other Editions
- Fault tolerant computer architecture
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