SACS
a cache simulator incorporating timing analysis with buffer and memory management
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Author
Publication
1994 - Naval Postgraduate School, Monterey, Calif, California
Language
English
Word Count
64,250 words, Guess
Page Count
257 pages
Identifiers
- Internet Archivesacscachesimulat00smit
- Open LibraryOL25601249M
Description
SACS is a cache simulator that provides the user with a wide range of timing information, in addition to providing typical information such as hit and miss rates. The SACS model includes read and write buffers, main memory, and cache memory. In addition. SACS supports a number of buffer and data forwarding policies, as well as the traditional block replacement, write. and write miss policies. SACS also includes a self-testing mode which can be used to debug the program after source-code modification.
Subjects
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