A primer on memory consistency and cache coherence

Alternate Titles

• Synthesis digital library of engineering and computer science.

Description

Many modern computer systems and most multicore chips (chip multiprocessors) support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both high level concepts as well as specific, concrete examples from real-world systems.

Subjects

Series Statement

• Synthesis lectures on computer architecture -- # 16

Links

• http://dx.doi.org/10.2200/S00346ED1V01Y201104CAC016

Other Editions

• A primer on memory consistency and cache coherenceElectronic resourceMorgan & Claypool2011-01-01
• A Primer on Memory Consistency and Cache Coherence2011-01-01
• Primer on Memory Consistency and Cache CoherenceMorgan & Claypool Publishers2020-01-01
• Primer on Memory Consistency and Cache CoherenceMorgan & Claypool Publishers2020-01-01
• Primer on Memory Consistency and Cache CoherenceMorgan & Claypool Publishers2020-01-01